1. Field of the Invention
The present disclosure relates to a flat panel display, and particularly, to storing data related to a driving voltage for driving a display panel, and a driving circuit thereof.
2. Background of the Invention
A flat panel display (FPD) is a display device which replaces a conventional cathode ray tube (CRT) display and is essentially used to implement a small-sized and light-weight system, such as a notebook computer, personal digital assistant (PDA), portable phone, and the like, as well as large-format systems such as a display monitor of a desktop computer and televisions. Current commercially available flat panel displays include a liquid crystal display LCD, a plasma display panel (PDP), an organic light emitting diode (OLED) display, and so on.
FIG. 1 is a view showing an example of a single pixel in the organic light emitting diode display among the above-mentioned flat panel displays. The display may include a plurality of scan lines SL and a plurality of data lines DL arranged in rows and columns that intersect at a plurality of pixels.
As shown, the pixel in FIG. 1 includes an organic light emitting diode D1, a switching thin film transistor ST and a driving thin film transistor DT, and is disposed in a region including a scan line SL supplying a scan signal, a data line DL supplying a data signal, and a driving voltage VDDEL supply.
A gate of the switching thin film transistor ST is connected to the scan line SL, a source thereof is connected to a gate of the driving thin film transistor DT, and a drain thereof is connected to the data line DL and functions as a switching element.
The gate of the driving thin film transistor DT is connected to the source of the switching thin film transistor ST and one end of a capacitor Cst, the source thereof is connected to the driving voltage VDDEL, and the drain thereof is connected to an anode of the organic light emitting diode D1. The driving thin film transistor DT functions as a driving element of the organic light emitting diode D1 by providing a driving current IOLED according to the voltage at its gate.
While the switching and driving thin film transistors ST and DT are depicted as PMOS transistors in FIG. 1, they may alternatively be formed as NMOS transistors.
One side of the capacitor Cst is connected to the source of the switching thin film transistor ST and the gate of the driving thin film transistor DT, and the other side thereof is connected to the driving voltage VDDEL.
The anode of the organic light emitting diode D1 is connected to the drain of the driving thin film transistor DT, and a cathode thereof is connected to a ground voltage VSS. An organic emission layer is provided between the anode and the cathode. The organic emission layer may include, for example, a hole injection layer, a hole transporting layer, an emission layer, an electron transporting layer, and an electron injection layer. Also, the organic emission layer may include, for example, an electron injection layer, an electron transporting layer, an emission layer, a hole transporting layer, and a hole injection layer.
The driving voltage VDDEL supplied to the pixel in the organic light emitting diode display having the above-mentioned structure may be set differently depending on a display panel; however, it is typically tightly regulated to a stable voltage level, for example, at 8.75 V. To this end, the flat panel display includes a power supply control unit for controlling the generation and supply of voltages used by the flat panel display in accordance with a power-up sequence based on preset data.
In particular, under the current trend towards highly integrated ICs and increasing complexity of driving, data required for a power-up sequence is stored in a memory, i.e., EEPROM (Electrical Erasable Programmable ROM). Accordingly, when the flat panel display is powered on, the data stored in the address of the EEPROM is read and the driving voltage VDDEL of the display panel is generated.
FIG. 2 is an equivalent circuit diagram showing an example of a internal structure of an EEPROM used for a conventional organic light emitting diode display.
As shown, the conventional EEPROM includes a first transistor T1 whose source is connected to a first input terminal connected to an external controller (not shown), whose gate is connected to a second resistor R2, and whose drain is connected to an output terminal, and a second transistor T2 whose source is connected to a second input terminal connected to the external controller, whose gate is connected to a first resistor R1, and whose drain is connected to the output terminal.
Although not shown, the above-mentioned output terminal is connected to a data storage cell in the EEPROM, and performs read, write, and erase operations on predetermined data by an output voltage.
The driving of the EEPROM with this structure will be explained. When a high-level driving enable signal VPP_HIGH is applied to the second input terminal, and a specific sequence signal, e.g., data write signal XWRITEB, is applied, the first and second transistors T1 and T2 become conductive. Accordingly, the data write signal XWRITEB is provided by a driving output voltage EXVPP to the data cell in the EEPROM through the output terminal, thereby performing read, write, and erase operations on data.
In accordance with the above-described operation, the system configurator configures a flat panel display by storing desired data in the EEPROM, then bonding other driving ICs of the flat panel display together onto a substrate by a typical SMT process, and then connecting the substrate to the display panel.
The above-mentioned SMT process is a process which applies considerable stress to each of the driving ICs; stress is applied even to each pin of the EEPROM. Especially, if stress is applied to a pin corresponding to an input terminal of the above-mentioned data write signal XWRITEB, a parasitic diode is formed between the above-mentioned first transistor T1 and the output terminal, and a predetermined current flows. Thus, the EEPOROM switches to erase mode even if the corresponding sequence is not input, and therefore data erasure may occur.
Accordingly, the driving voltage VDDEL provided to the display panel is output not at the preset voltage level (e.g., 8.75V) but at an arbitrary voltage level (e.g., up to 14V), thereby leading to malfunctioning of the display panel.